Integrated circuit (“IC”) designers desire to increase the level of integration, or density, of features within an IC by reducing the size of the features and by reducing the separation distance between neighboring features on a substrate. The distance between identical points in neighboring features is referred to in the industry as “pitch” and is conventionally measured as the center-to-center distance between the features. The pitch is about equal to the sum of a width of the feature and a width of a space separating the feature from the neighboring feature. With the pressure to reduce feature sizes and pitch, pitch reduction processes have been developed.
A conventional pitch reduction process, which is also sometimes implemented as a “pitch multiplication” process is illustrated in FIGS. 1A-1G. Pitch multiplication is used to form at least two features in a target material, such as a substrate, for each feature formed in a mask, such as a resist material, overlying the target material. As illustrated in FIG. 1A, an array of first features 10 is formed in the resist material overlying the target material 20. The first features 10 are typically formed having a minimum feature size (“F”). First features 10 are separated from each other by first spaces 12. First features 10 and first spaces 12 have a first pitch, which is labeled in FIG. 1A as “X.” A spacer material 30 is formed over first features 10 and target material 20, as illustrated in FIG. 1B. The spacer material 30 reduces the width of first spaces 12, forming first spaces 12′. Spacer material 30 is anisotropically removed to form spacer sidewalls 36, as illustrated in FIGS. 1C and 1D, where FIG. 1D is a cross-sectional view along line a-a in FIG. 1C. As illustrated in FIG. 1C, which is a top view of the illustration in FIG. 1D, spacer sidewalls 36 surround each of first features 10. First features 10 are removed from target material 20, forming freestanding spacer sidewalls 36, as illustrated in FIG. 1E. The removal of first features 10 produces second spaces 18 surrounded by spacer sidewalls 36. The spacer sidewalls 36, second spaces 18, and first spaces 12′ are used as a mask to pattern the target material 20. The pattern in the target material 20 includes second features 32 (see FIG. 1G), such as lines or trenches, that correspond to second spaces 18 and first spaces 12′ and third spaces 34 (see FIG. 1G) that correspond to the spacer sidewalls 36. The second features 32 and third spaces 34 in the target material 20 have a pitch about one-half of the first pitch, which is labeled in FIG. 1E as “X/2.” Where the width X included one first feature 10 and first space 12 before the pitch doubling process, width X now includes two second features 32 and two third spaces 34. While the pitch is actually halved in the example above, this reduction in pitch is conventionally referred to as pitch “doubling.” This conventional terminology is retained herein.
In this pitch doubling process, ends of second spaces 18 are isolated by spacer sidewalls 36. However, ends of first spaces 12′ are not isolated. As illustrated in FIG. 1F, one approach to isolating first spaces 12′ has been to form a mask 40 over the ends of first spaces 12′, second spaces 18, and spacer sidewalls 36. Mask 40 isolates first spaces 12′, while spacer sidewalls 36 serve as a mask to pattern target material 20, as illustrated in FIG. 1G. Since a second lithography process using mask 40 is used to block an etch when forming the patterned target material 20, two masking levels are used in the pitch doubling process illustrated in FIGS. 1A-1G.
A need exists in the art for methods of isolating the second spaces formed between features without using a second masking level.